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Comp 304: Component And Design Techniques For Digital Systems Question Paper
Comp 304: Component And Design Techniques For Digital Systems
Course:Bachelor Of Science In Computer Science
Institution: Chuka University question papers
Exam Year:2011
CHUKA UNIVERSITY
KAPKWEN@CU2014(0712 880 531)
UNIVERSITY EXAMINATIONS
THIRD YEAR EXAMINATION FOR THE AWARD OF THE BACHELOR OF SCIENCE IN COMPUTER SCIENCE
COMP 304: COMPONENT AND DESIGN TECHNIQUES FOR
DIGITAL SYSTEMS
STREAM: BSc. (Comp. Science) Y3 S1 TIME: 2 HOURS
DAY/DATE: MONDAY 1/8/2011 2.30P.M. – 4.30 P.M.
INSTRUCTIONS:
1. Answer question ONE and any other TWO questions
2. Marks are awarded for clear and concise answers
Question One Compulsory (30 marks)
(a) Briefly describe the functions of the following digital devices.
i. Adders [2 mark]
ii. Decoders [2 mark]
iii. Multiplexers [2 mark]
iv. PAL [2 mark]
(b) For the following function.
i. List all prime implicants, indicating which are essential. [3 marks]
ii. Show the minimum sum of products expression(s). [3 marks]
F (A, B, C, D) = Sm (0, 1, 4, 5, 7, 8, 10, 13, 14, 15)
(c) Find the minimum sum of production expression for the following function.
[4 marks]
F (W, X, Y, Z) = Sm (1, 3, 5, 6, 7, 13, 14) + S d (8, 10, 12)
The function has 2 solutions, also show the second expression that satisfies the requirement. [2 mark]
(d) Design a half adder circuit using only 2-input NAND gates.
[3 marks]
(e) With the aid of a diagram show how the following logic function can be implemented
on a PAL device [4 marks]
F = (A+B’+C) (A’+C)
(f) Design a Mealy system whose output is 1 for every third 1 input (not necessarily
consecutive ). [3 marks]
Question Two (20 marks)
The figure below shows a chocolate vending machine controller that accepts either 10Ksh or 20Ksh coins and vends chocolate bars, each costing 30Ksh. When a 10Ksh or a 20Ksh coin is inserted, K10 or K20 will respectively go high for one clock cycle shortly after the rising edge of the clock signal CLK. Only one coin can be inserted at any one time. Whenever the signal VEND is high, a chocolate bar is dispensed from the vending machine on the next clock cycle. Whenever the signal CHANGE is high, a 10K coin is returned on the next clock cycle.
a) Design a finite state machine (FSM) in the form of a state diagram to implement the vending machine controller. State clearly any assumptions made. [8 marks]
b) Draw the transition table for your state machine. [4 marks]
c) Derive minimized Boolean equations for your FSM. [8 marks]
Question Three (20 marks)
A circuit has four inputs P, Q, R, and S representing the natural binary numbers 00002 = 010 to 10112 = 1110. P is the most significant bit.
The input code represents a month of the year with 0000 = January, 0001 = February, …, and 1011 = December. The circuit has output, X, that is true if the number represented by the input is a month with 31 days. Note that months with 31 days are January, March, July, August, October and December.
a) Construct a truth table for this circuit. [5 marks]
b) Hence(or otherwise) obtain a Boolean expression for X in terms of inputs P, Q, R and S
[6 marks]
c) Give the circuit diagram of an arrangement of AND, OR and NOT gates to implement the circuit. [6 marks]
d) Modify the Boolean expression of part b so that the output is true if the month has 31 days or is February (which can be 28 or 29 days). [3 marks]
Question Four (20 marks)
a) List the design steps that are required to design a synchronous counter. [6 marks]
b) Using falling-edge triggered, resetable, J-K flip-flops, design an asynchronous binary counter which counts the sequence
0, 1, 2, …, 10, 11, 0, 1, 2, …
Show a labeled diagram for the counter. [7 marks]
c) Sketch a timing diagram of duration 14 counts and indicate the position of any glitches. [4 marks]
d) State which device parameter limits the maximum speed of operation of the counter. Suggest a typical value for this parameter and hence calculate the maximum speed of operation for this suggested value. [3 marks]
Question Five (20 marks)
For the function:
f = A’B’D’ + A’BD + BC’D + BCD + AB’C + AB’C’D’
a) Construct a Karnaugh map and use it to find a minimum sum of products expression
for f. [4 marks]
b) Draw a logic circuit for the minimized expression using only AND, OR and NOT
gates. [4 marks]
c) Manipulate the expression into a suitable form and hence draw a logic circuit using
only NAND gates. [5 marks]
d) Manipulate the expression into a suitable form and hence draw a logic circuit using
only NOR gates. [5 marks]
e) Compare the relative merits of the logic circuit solutions to parts c) and e). [2 marks]
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KAPKWEN@CU2014(0712 880 531)
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