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Sce 510: Cad Application Question Paper

Sce 510: Cad Application

Course:Master Of Science

Institution: Kenyatta University question papers

Exam Year:2008

KENYATTA UNIVERSITY
UNIVERSITY EXAMINATIONS 2008/2009
FIRST SEMESTER EXAMINATION FOR THE DEGREE OF MASTER OF
SCIENCE
SCE 510: CAD APPLICATION
DATE: Monday 1st December, 2008 TIME: 2.00 p.m. – 4.00 p.m.
INSTRUCTIONS
Answer question one and any other TWO questions.
Question 1 – (30 marks) compulsory
a) Define the term Testbench [2 marks]
b) Standardization in electronics industry is vital, discuss. [4 marks]
c) State any CAD application software used in the following fields of engineering
(i) Architectural
(ii) Mechanical
d) Discuss the general CAD system architecture. [8 marks]
e) Define the terms: design model and design prototype. [2 marks]
f) Differentiate between Simulation and synthesis in electronic design.
[4 marks]
g) Discuss the benefits of Electronics Computer Aided Design. [8 marks]
Question 2 – (20 marks)
a) Discuss the limitations of Computer Aided Design tools. [8 marks]
b) Compare and contrast Schematic design capture and Language Description
capture in Electronics circuit design automation. [8 marks]
c) Design communication in electronics circuits is done via symbols; draw the
electronics standard symbols for the following components:
(i) Silicon controlled rectifier
(ii) PNP transistor
(iii) TRIAC diode
(iv) Darlington pair [4 marks]
2
Question 3 – (20 marks)
a) Discuss the Electronics system development process using CAD tools.
[8 marks]
b) Future Tech is company that deals with VLSI circuit design, it exports designs to various fabricating companies like lucent technologies. IBM etc. the company would like to purchase a new CAD tool that will replace the existing. You have been appointed as the director of the company.
i) State four reasons why you would be thrilled to replace the current CAD tool? [4 marks]
ii) Explain four strategic measures you would take before replacing the existing CAD tool. [8 marks]
Question 4 – (20 marks)
a) Write a VHDL program to capture the RTL design of a 4 bit parallel ADDER circuit. [12 marks]
b) A system is mathematically model as follows:
x(n) = cos (0.04?n) + 0.2?(n), 0 ? n ? 50
Write an M-file that emulates the system. [8 marks]
Question 5 – (20 marks)
a) State the difference between HIGH level languages and hardware description languages. [2 marks]
b) With respect to VHDL, define the following terms:
i) Entity
ii) Architecture
iii) Package
iv) Configuration
v) Driver [5 marks]
c) Discuss the EIA industry standard resistor color coding. [8 marks]
d) Draw the EIA/IEEE standard modern logic symbols equivalent of
OR, AND, NAND, NOR, XOR [5 marks]
+++++++++++++++++

Sce 510: Cad Application Question Paper

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