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Engineering Electronics Question Paper

Engineering Electronics

Course:Bachelor Of Science In Engineering

Institution: Kenyatta University question papers

Exam Year:2008

KENYATTA UNIVERSITY
UNIVERSITY EXAMINATIONS 2008/2009
FIRST SEMESTER EXAMINATION FOR THE DEGREE OF BACHELOR OF
SCIENCE MANUFACTURING AND BACHELOR OF SCIENCE ENERGY ENGINERING
SET 300: ENGINEERING ELECTRONICS
DATE: Monday 24th November, 2008 TIME: 8.00 a.m. – 10.00 a.m.
================================================================================
INSTRUCTIONS:
(i) There are a total of Five questions.
(ii) Select any Three questions.
(iii) Define all symbols used.
(iv) Marks will be awarded for procedure, methodologies used and not necessarily the
final answer.

1. (a) (i) Derive an expression for forward current gain and leakage current of
Common Emitter configuration in terms of current gain and leakage
current of Common Base configuration. (8 Marks)
(ii) If a = 0.99 and CBO I = 5µA, calculate ß and CEO I . (4 Marks)

(b) Fig.Q1 is a single battery biasing circuit. If E I =2 mA, B I =50µA, BE V = 0.2V,
BB V =10V, 1 R =1KO 3 R =10KO, calculate:-
(i) Voltage across 3 R . (2 Marks)
(ii) Voltage across 2 R . (2 Marks)
(iii) Current through 2 R . (2 Marks)
(iv) Value of 2 R . (2 Marks)

2. (a) Using relevant energy diagrams, demonstrate thorough understanding of
forward and reverse biased p-n junction. (12 Marks)

(b) Fig.Q2b gives the characteristics of an npn Transistor. Interpreted the
characteristics, clearly indicating its different regions and their relevance. (5 Marks)

(c) Fig. Q2c is a pnp Transistor circuit. If BB V = CC V = -30volts, calculate CE V ,
C V and E V . (3 Marks)

3. (a) A pnp Transistor has the following Load Line characteristics:-
CMAX I = 8mA, CQ I =4.5mA, BQ I =45µA and CEQ V =7.5volts.
(i) Explain what the data means. (3 Marks)
(ii) Draw the Load Line and explain its use. (2 Marks)

(b) If the transistor in (a) is biased with a BB V / CC V of 20volts, design a single stage
RC Coupled audio amplifier capable of supplying a 1mA peak signal current
into its collector load resistance. (15 Marks)

4. (a) Consider a two input positive logic diode OR gate circuit with R V =0. The
inputs are square waves given in Fig.Q4. Assume ideal diodes ( f R =0, r R = 8,
V =0 and S R =0.
(i) Draw the equivalent circuit for the OR gate. (4 Marks)
(ii) Sketch the output waveform if the ratio of the amplitude of 2 V to 1 V is:-
(a) 2. (3 Marks)
(b) ½. (3 Marks)

(b) Consider a two input positive logic diode AND gate circuit with R V = 10V,
R=10O and S R = 0. The inputs are given in Fig.Q4.
(i) Draw the equivalent circuit. (4 Marks)
(ii) Sketch the output waveform if the ratio of 2 V to 1 V is:-
(a) 2. (3 Marks)
(b) 1. (3 Marks)

5 (a) (i) Translate the hardware depicted in Fig.Q5 into a Boolean expression.
(3 Marks)
(ii) Compute the value of the output if A=0, B=0, C=1 and D=1. (2 Marks)

(b) (i) Convert Decimal 1985 to Hexadecimal. (3 Marks)
(ii) Express 10 45 in Excess-3 Code. (2 Marks)
(c) (i) Draw a Diode OR circuit for negative logic. (5 Marks)
(ii) Explain how the Diode OR circuit in (c) (i) functions. (5 Marks)

Engineering Electronics Question Paper

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